Technische Informatik

Since the principle of active noise control was proposed for the first time in the year 1936, the implementation of these ideas always lagged behind in time due to a lack of sufficiently performant computers. With the introduction of digital computers and their rapid advancement until today, applied resarch projects and commercial products became well-established. However, active noise control applied to complex and large-scale structures is still limited by suitable implementation technologies to this date. The suitability is foremost characterized by raw processing power, but also by the resulting processing delay and energy efficiency. Besides, some research suggests that the noise reduction performance of well-established applications in active noise control can also benefit from additional computational power. It is the goal of this thesis to narrow this technology-based gap for a wide range of active noise control applications by optimizing existing control algorithms down to the hardware level or rather the register-transfer level. The custom hardware architectures are realized using field-programmable gate arrays (FPGAs) and provide generic parameters to adjust the algorithm and the internal processing architecture to favor various applications. In case of the feedback FxLMS architecture, a short processing delay is achieved that is independent of any filter length. The performance of the proposed hardware architectures are validated against established software reference systems on experimental setups using identical configurations.The resources of different FPGA platforms are then fully utilized to indicate the corresponding benefits in terms of noise reduction performance for these experimental setups. For the feedback FxLMS algorithm, the most computational demanding, synthesized configuration uses 11 error sensors, 11 secondary sources and filter orders of 2049 at a sampling rate of 48 kHz. For this configuration, this translates to delay times well below 1 μs. On multiple practical applications, the results show an additional noise reduction performance of up to 12 dB compared to the maximum possible configurations of the software reference.

The most used algorithm in active noise control (ANC) applications is the filtered-x least mean square (FxLMS). For large scale systems with multiple inputs and outputs the computational demand of the FxLMS is rising rapidly. Conventional solutions, running on digital signal processors (DSPs), have limitations in parallel computing. In this work a parameterizable multiple input-multiple output (MIMO) feedback FxLMS architecture for field-programmable gate array (FPGA) platforms is presented that can easily be optimized for high-performance or resource efficient computation. The implementation is validated in a real-time practical application using an active headrest with 2 x 2 channels. The noise reduction is evaluated over various configurations with increasing performance and the respective synthesis results are presented. Here the noise reduction does benefit from the additional computational performance gains. An additional configuration with 11 x 11 channels and filter lengths of 2049 at a sample rate of 40 kHz is shown as a benchmark on high-end FPGAs.

Field Programmable Gate Arrays (FPGAs) support the change of its hardware functionality, even after production. They are already very common in research and industry. Their main field of application is hardware prototyping and High Performance Computing (HPC). This work suggests an extension of this field of application, towards general-purpose computing, such as standard personal computers. Typical applications, which will profit from this extensions, are image and video processing and cryptographic applications and also the simulation of physical systems. The requirement analysis, for the development process of such a system and the FPGA layout, suggests the importance of flexibility and the dynamic runtime reconfiguration of hardware components without interfering with running computations. A good operating system support is also very important. The granularity problem of runtime reconfigurable design flow is identified as one major problem. It arises from the fact that the runtime reconfigurable design flows at the moment require a decision about the number and size of the reconfigurable components at their first step. This work presents two solutions to the granularity problem. Furthermore, the work presents a multi FPFA framework. It implements one of the solutions to the granularity problem and is optimized for the use in a general-purpose environment. This Multicore Reconfiguration Platform (MRP) is easily extensible by adding FPGA boards at runtime. The evaluation of the MRP is done using the dimensions time and area and an example application. The example application consist of a small microprocessor core.

The anti-lock braking system (ABS) is a widely used vehicle stabilization system in automobiles. The required speed information of the vehicle wheels for the ABS control are measured by wheel speed sensors, which are located at each vehicle wheel. These sensors provide electrical signals to the ABS control unit. For the function of anti-lock braking systems, it is necessary that the signals are highly reliable and available. The present work deals with the development of an extended state detection for wheel speed sensors. These sensors are magnetic sensors that operate either inductive-based, Hall-based or on magnetoresistive-based. In this work, the focus is on the wheel speed sensors based on the anisotropic magnetoresistive effect (AMR). From the literature it is known that the AMR effect outside a specified operating point has a highly non-linear behavior. This results in the vehicle operation of the AMR sensor in certain positions to distortions in the sensor signal. In this work, critical sensor positions were determined by a metrological analysis of the entire system from the encoder and sensor. The sensor signals show in these areas special characteristic distortion. The non-linear behavior of the AMR sensors will be described with a 2D sensor characteristic diagram. The diagrams of different AMR sensors were determined by measuring, with a newly developed method. The magnetic system of AMR sensor and encoder also has non-linear characteristics. For the analysis of magnetic field strengths acting on the AMR-sensor, magneto-static field simulations were performed. The determined field strengths from the simulations enable the synthesis of an electrical sensor output voltage across the sensor diagram. The method of synthesis shows the causes of signal distortion occurring. The distortions in the sensor signal can be evaluated over the spectrum. In the spectrum harmonic frequencies of the fundamental occur. Since the frequency of the sensor signal is subject to continuous variations in the driving mode, this made the development of an adaptive sampling algorithm required. It allows the use of the discrete Fourier transform to determine the harmonic components. For the degree of distortion of the sensor signal indicators have been defined which are based on the known THD. For the integration of harmonic analysis and the calculation of the indicators directly in a sensor low power consumption and a minimum chip area are required. To achieve these parameters optimized architectures for digital signal processing have been developed and implemented. As part of the experimental evaluation platforms were developed based on microcontrollers and FPGA for the evaluation of algorithms. One of the developed algorithms has been integrated in mixed-signal ASIC based on CMOS technology. In the final chapter, these experimental platforms are presented and evaluated.

Nowadays, FPGAs are commonly used to take advantage of their reconfigurability as accelerator units. Moores Law still predicts increasing transistor densities for integrated circuits. Some Authors predict, that this will result in the general usage of reconfigurable areas in future computer architectures. This thesis proposes to combine those reconfigurable areas with the idea of system virtual machines. The capability of reconfigurable hardware to provide software as needed is exploited to support system virtual machines with their own hardware on demand. Firstly, the architectural requirements to take advantage of reconfigurable areas for the purpose of supporting virtual machines are discussed theoretically for the important parts of a computer: main memory, devices and processors. As a second step, a proof of concept demonstrator is developed to proof the theoretically discussed advantages of such a FPGA supported virtualization system. The ability to perform dynamic and partial reconfiguration of a FPGA is used to implement both, the static (for the host system) and the reconfigurable parts (for the guest systems) of the hardware of such a virtualization system. The demonstrator not only includes hardware, but also an full fledged operating system (an adapted Linux kernel, able to be executed on the hardware) including all necessary device drivers. Finally, the theoretically expected advantages of a FPGA based virtualization system over conventional virtualization systems are measured and therefore shown on base of the proof of concept demonstrator. Furthermore remaining problems and possible solutions will be presented.

Konventionelle fest verdrahtete Hardware zeichnet sich durch ein hohes Maß an Flexibilität aus, indem sie anhand von Anwendungssoftware eine Vielfalt von Problemlösungen ermöglicht. Trotz ihrer stetig steigenden Leistungsfähigkeit genügt sie für zeitkritische Anwendungen jedoch nicht immer den gestellten Anforderungen. In solchen Fällen werden meistens sog. Application Specifi Integrated Circuits (ASICs) verwendet. Dieser Art von Hardware fehlt jedoch die Flexibilität, für unterschiedliche Anwendungen eingesetzt werden zu können. Field-Programmable-Gate Arrays (FPGAs) vereinigen die Vorteile beider Hardware-Plattformen: Leistungsfähigkeit und Flexibilität. Dennoch bleiben aufgrund des bisherigen damit verbundenen hohen Hardware- und Software-Aufwands (z.B. Hardware/Software-Partitionierung) der Anwenderkreis und die Anwendungsgebiete sehr beschränkt. ----- Die vorliegende Arbeit untersucht einen evolutionären Ansatz, in wieweit die Vorzüge rekonfigurierbarer Hardware (FPGA) in Prozessorarchitekturen eingesetzt werden können. Im Gegensatz zu den bisherigen Ansätzen sollten dabei die Kompatibilität mit herkömmlichen Rechensystemen gewährleistet sein und bestehende Hardware- und Software-Werkzeuge weiterhin verwendbar bleiben. Zu diesem Zweck wurde im Rahmen dieser Arbeit das Modell einer rekonfigurierbaren Mikroarchitektur entwickelt. Anhand von Software-Simulationen wurden unterschiedliche Möglichkeiten der Hardware-Rekonfiguration auf ihr Leistungspotenzial hin überprüft. Daraufhin wurde mit Blick auf die hohe Komplexität eines modernen Prozessors einerseits und die Einschränkungen heutiger Entwurfswerkzeuge andererseits ein realitätsnahes Modell einer partiell und dynamisch rekonfigurierbaren Mikroarchitektur vorgezogen und auf einem FPGA implementiert. Dabei wurden vordefinierte Hardware-Konfigurationen während der Programmausführung und in Abhängigkeit der anwendungsspezifischen Hardware-Anforderungen ausgetauscht. Die Mikroarchitektur implementiert den ARM-Thumb-Befehlssatz anhand einer fünfstufigen superskalaren Pipeline. Die erzielten Ergebnisse ermutigen zur Weiterführung des entwickelten Konzeptes, das bereits durch eine auf dieser Arbeit basierende Weiterentwicklung bestätigt wurde.