Hardware acceleration of active noise control algorithms
Publication date
2023-05-31
Document type
PhD thesis (dissertation)
Author
Klemd, Alexander
Advisor
Referee
Granting institution
Helmut-Schmidt-Universität/Universität der Bundeswehr Hamburg
Exam date
2023-05-24
Organisational unit
Publisher
Universitätsbibliothek der HSU/UniBw H
Part of the university bibliography
✅
Language
English
DDC Class
629 Andere Fachrichtungen der Ingenieurwissenschaften
Keyword
FPGA
VHDL
ANC
Feedback
FxLMS
MIMO
Abstract
Since the principle of active noise control was proposed for the first time in the year 1936, the implementation of these ideas always lagged behind in time due to a lack of sufficiently performant computers. With the introduction of digital computers and their rapid advancement until today, applied resarch projects and commercial products became well-established. However, active noise control applied to complex and large-scale structures is still limited by suitable implementation technologies to this date. The suitability is foremost characterized by raw processing power, but also by the resulting processing delay and energy efficiency. Besides, some research suggests that the noise reduction performance of well-established applications in active noise control can also benefit from additional computational power.
It is the goal of this thesis to narrow this technology-based gap for a wide range of active noise control applications by optimizing existing control algorithms down to the hardware level or rather the register-transfer level. The custom hardware architectures are realized using field-programmable gate arrays (FPGAs) and provide generic parameters to adjust the algorithm and the internal processing architecture
to favor various applications. In case of the feedback FxLMS architecture, a short processing delay is achieved that is independent of any filter length. The performance of the proposed hardware architectures are validated against established software reference systems on experimental setups using identical configurations.The resources of different FPGA platforms are then fully utilized to indicate the
corresponding benefits in terms of noise reduction performance for these experimental setups. For the feedback FxLMS algorithm, the most computational demanding, synthesized configuration uses 11 error sensors, 11 secondary sources and filter orders of 2049 at a sampling rate of 48 kHz. For this configuration, this translates to delay times well below 1 μs. On multiple practical applications, the results show an additional noise reduction performance of up to 12 dB compared to the maximum possible configurations of the software reference.
It is the goal of this thesis to narrow this technology-based gap for a wide range of active noise control applications by optimizing existing control algorithms down to the hardware level or rather the register-transfer level. The custom hardware architectures are realized using field-programmable gate arrays (FPGAs) and provide generic parameters to adjust the algorithm and the internal processing architecture
to favor various applications. In case of the feedback FxLMS architecture, a short processing delay is achieved that is independent of any filter length. The performance of the proposed hardware architectures are validated against established software reference systems on experimental setups using identical configurations.The resources of different FPGA platforms are then fully utilized to indicate the
corresponding benefits in terms of noise reduction performance for these experimental setups. For the feedback FxLMS algorithm, the most computational demanding, synthesized configuration uses 11 error sensors, 11 secondary sources and filter orders of 2049 at a sampling rate of 48 kHz. For this configuration, this translates to delay times well below 1 μs. On multiple practical applications, the results show an additional noise reduction performance of up to 12 dB compared to the maximum possible configurations of the software reference.
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