Publication: Low-Latency FIR Filter Structures Targeting FPGA Platforms
cris.customurl | 6527 | |
cris.virtual.department | Technische Informatik | |
cris.virtual.department | Helmut-Schmidt-Universität / Universität der Bundeswehr Hamburg | |
cris.virtual.department | Technische Informatik | |
cris.virtual.department | Allgemeine Nachrichtentechnik | |
cris.virtual.department | Allgemeine Nachrichtentechnik | |
cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
cris.virtual.departmentbrowse | Technische Informatik | |
cris.virtual.departmentbrowse | Helmut-Schmidt-Universität / Universität der Bundeswehr Hamburg | |
cris.virtual.departmentbrowse | Technische Informatik | |
cris.virtual.departmentbrowse | Allgemeine Nachrichtentechnik | |
cris.virtual.departmentbrowse | Allgemeine Nachrichtentechnik | |
cris.virtual.departmentbrowse | Technische Informatik | |
cris.virtual.departmentbrowse | Helmut-Schmidt-Universität / Universität der Bundeswehr Hamburg | |
cris.virtual.departmentbrowse | Technische Informatik | |
cris.virtual.departmentbrowse | Allgemeine Nachrichtentechnik | |
cris.virtual.departmentbrowse | Allgemeine Nachrichtentechnik | |
cris.virtual.departmentbrowse | Technische Informatik | |
cris.virtual.departmentbrowse | Helmut-Schmidt-Universität / Universität der Bundeswehr Hamburg | |
cris.virtual.departmentbrowse | Technische Informatik | |
cris.virtual.departmentbrowse | Allgemeine Nachrichtentechnik | |
cris.virtual.departmentbrowse | Allgemeine Nachrichtentechnik | |
cris.virtualsource.department | 7f605a50-f67e-4796-9228-3d3d36ee7884 | |
cris.virtualsource.department | 7dcd0915-c0f3-4a89-a98e-5c391eb07f57 | |
cris.virtualsource.department | 7dcd0915-c0f3-4a89-a98e-5c391eb07f57 | |
cris.virtualsource.department | 75ed0627-e101-4d10-b901-c3fb6a3e7e6d | |
cris.virtualsource.department | fc2edc53-45cc-4aec-8616-dae53916a798 | |
cris.virtualsource.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
dc.contributor.author | Eckert, Marcel | |
dc.contributor.author | Klauer, Bernd | |
dc.contributor.author | Rivera Benois, Piero Iared | |
dc.contributor.author | Nowak, Patrick | |
dc.contributor.author | Zölzer, Udo | |
dc.date.issued | 2018 | |
dc.description | HEART 2018 | |
dc.description.version | NA | |
dc.identifier.citation | Enthalten in: HEART 2018. - Toronto : University of Toronto, 2018 | |
dc.identifier.doi | 10.1145/3241793.3241807 | |
dc.identifier.uri | https://openhsu.ub.hsu-hh.de/handle/10.24405/6527 | |
dc.language.iso | en | |
dc.publisher | University of Toronto | |
dc.relation.orgunit | Technische Informatik | |
dc.relation.orgunit | Allgemeine Nachrichtentechnik | |
dc.rights.accessRights | metadata only access | |
dc.title | Low-Latency FIR Filter Structures Targeting FPGA Platforms | |
dc.type | Conference paper | |
dcterms.bibliographicCitation.originalpublisherplace | Toronto | |
dspace.entity.type | Publication | |
hsu.uniBibliography | ✅ |