Now showing 1 - 2 of 2
  • Publication
    Metadata only
    Print your gadget: New channels for manufacturers using locally available 3D printers
    (Helmut-Schmidt-Universität / Universität der Bundeswehr Hamburg, Laboratorium Fertigungstechnik, 2016) ;
    Haase, Jan
    ;
    ; ; ;
    Redlich, Tobias
    ;
    Moritz, Manuel
  • Publication
    Open Access
    Multicore Reconfiguration Platform - A Research and Evaluation FPGA Framework for Runtime Reconfigurable Systems
    (Universitätsbibliothek der HSU / UniBwH, 2015) ; ;
    Helmut-Schmidt-Universität / Universität der Bundeswehr Hamburg
    ;
    Field Programmable Gate Arrays (FPGAs) support the change of its hardware functionality, even after production. They are already very common in research and industry. Their main field of application is hardware prototyping and High Performance Computing (HPC). This work suggests an extension of this field of application, towards general-purpose computing, such as standard personal computers. Typical applications, which will profit from this extensions, are image and video processing and cryptographic applications and also the simulation of physical systems. The requirement analysis, for the development process of such a system and the FPGA layout, suggests the importance of flexibility and the dynamic runtime reconfiguration of hardware components without interfering with running computations. A good operating system support is also very important. The granularity problem of runtime reconfigurable design flow is identified as one major problem. It arises from the fact that the runtime reconfigurable design flows at the moment require a decision about the number and size of the reconfigurable components at their first step. This work presents two solutions to the granularity problem. Furthermore, the work presents a multi FPFA framework. It implements one of the solutions to the granularity problem and is optimized for the use in a general-purpose environment. This Multicore Reconfiguration Platform (MRP) is easily extensible by adding FPGA boards at runtime. The evaluation of the MRP is done using the dimensions time and area and an example application. The example application consist of a small microprocessor core.