Prof. Dr. Bernd Klauer

Academic degrees
Univ.-Prof. Dr. phil. nat. habil.
 
Full Name
Klauer, Bernd
 
Credit Name
Prof. Dr. Bernd Klauer
 
 

Publications

Results 1-19 of 19 (Search time: 0.012 seconds).

Issue DateTitleAuthor(s) 
12017Wireless sensor/actuator device configuration by NFC with secure key exchangeKlauer, Bernd ; Meyer, Dominik ; Haase, Jan ; Eckert, Marcel 
22016Wireless sensor/actuator device configuration by NFCHaase, Jan ; Meyer, Dominik ; Eckert, Marcel ; Klauer, Bernd 
32020Validation and performance anaysis of a parameterizable normalized feedback FxLMS archtiecture for FPGA platformsTimmermann, Johannes ; Klemd, Alexander ; Hanselka, Jonas ; Sachau, Delf  ; Klauer, Bernd 
42016System virtual machines in the context of reconfigurable computingEckert, Marcel ; Haase, Jan ; Meyer, Dominik ; Klauer, Bernd 
52016Print your gadgetKlauer, Bernd ; Haase, Jan ; Eckert, Marcel ; Meyer, Dominik 
62016Operating System Concepts for Reconfigurable ComputingEckert, Marcel ; Meyer, Dominik ; Klauer, Bernd ; Haase, Jan 
72017New attack vectors for building automation and IoTMeyer, Dominik ; Haase, Jan ; Eckert, Marcel ; Klauer, Bernd 
82018Low-Latency FIR Filter Structures Targeting FPGA PlatformsRivera Benois, Piero Iared ; Nowak, Patrick ; Zölzer, Udo ; Eckert, Marcel ; Klauer, Bernd 
92018Low-Latency FIR Filter Structures Targeting FPGA PlatformsEckert, Marcel ; Klauer, Bernd ; Rivera Benois, Piero Iared ; Nowak, Patrick ; Zölzer, Udo 
102013Hardware Based Security Enhanced Direct Memory AccessEckert, Marcel ; Podebrad, Igor ; Klauer, Bernd 
112016Generic operating-system support for FPGAsMeyer, Dominik ; Haase, Jan ; Eckert, Marcel ; Klauer, Bernd 
122018Experimental results of the effect of increased filter length and sample rate of a feedback active noise control system with FxLMS-algorithm implemented in VHDLHanselka, Jonas ; Klemd, Alexander ; Sachau, Delf  ; Klauer, Bernd 
132016Digital Hardware Synthesis as a Clud ServiceHaase, Jan ; Meyer, Dominik ; Eckert, Marcel ; Klauer, Bernd 
142017Comparison and evaluation of cache parameters for softcores on FPGAsEckert, Marcel ; Meyer, Dominik ; Klauer, Bernd ; Haase, Jan 
152016CloudSynthMeyer, Dominik ; Haase, Jan ; Eckert, Marcel ; Klauer, Bernd 
162015Clock speed optimization of runtime reconfigurable systems by signal latency measurementMeyer, Dominik ; Haase, Jan ; Eckert, Marcel ; Klauer, Bernd 
172016Architectural requirements for constructing hardware supported sandboxesEckert, Marcel ; Haase, Jan ; Meyer, Dominik ; Klauer, Bernd 
182016A threat-model for building and home automationMeyer, Dominik ; Haase, Jan ; Eckert, Marcel ; Klauer, Bernd 
192021A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA PlatformsKlemd, Alexander ; Klauer, Bernd ; Timmermann, Johannes ; Sachau, Delf