Technische Informatik

Email Alert RSS Feed

Organization Name

Director

Klauer, Bernd

Parent Org Unit

Fakultät für Elektrotechnik

Status

Active Organization Unit

Website/URL

Professur für Technische Informatik

Results 1-10 of 10 (Search time: 0.008 seconds).

	Issue Date	Title	Author(s)
1	2005	Zum Einsatz von rekonfigurierbarer Hardware in Prozessorarchitekturen	Niyonkuru, Adronis
2	2020	Validation and performance anaysis of a parameterizable normalized feedback FxLMS archtiecture for FPGA platforms	Timmermann, Johannes ; Klemd, Alexander ; Hanselka, Jonas ; Sachau, Delf ; Klauer, Bernd
3	2015	Systemarchitektur und Signalverarbeitung für die Diagnose von magnetischen ABS-Sensoren	Krey, Martin
4	2016	Print your gadget: New channels for manufacturers using locally available 3D printers	Klauer, Bernd ; Haase, Jan ; Eckert, Marcel ; Meyer, Dominik
5	2015	Multicore Reconfiguration Platform - A Research and Evaluation FPGA Framework for Runtime Reconfigurable Systems	Meyer, Dominik
6	2018	Low-Latency FIR Filter Structures Targeting FPGA Platforms	Eckert, Marcel ; Klauer, Bernd ; Rivera Benois, Piero Iared ; Nowak, Patrick ; Zölzer, Udo
7	2023	Hardware Acceleration of Active Noise Control Algorithms	Klemd, Alexander
8	2014	FPGA-Based System Virtual Machines	Eckert, Marcel
9	2018	Experimental results of the effect of increased filter length and sample rate of a feedback active noise control system with FxLMS-algorithm implemented in VHDL	Hanselka, Jonas ; Klemd, Alexander ; Sachau, Delf ; Klauer, Bernd
10	2021	A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms	Klemd, Alexander ; Klauer, Bernd ; Timmermann, Johannes ; Sachau, Delf

Results 1-7 of 7 (Search time: 0.005 seconds).

	Issue Date	Title	Author(s)
1	2021	A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms	Klemd, Alexander ; Klauer, Bernd ; Timmermann, Johannes ; Sachau, Delf
2	2018	Experimental results of the effect of increased filter length and sample rate of a feedback active noise control system with FxLMS-algorithm implemented in VHDL	Hanselka, Jonas ; Klemd, Alexander ; Sachau, Delf ; Klauer, Bernd
3	2021	Low latency real-time deflagration detection using a Field Programmable Gate Array	Eckert, Marcel ; Krooß, Jakob ; Klauer, Bernd ; Fay, Alexander
4	2018	Low-Latency FIR Filter Structures Targeting FPGA Platforms	Eckert, Marcel ; Klauer, Bernd ; Rivera Benois, Piero Iared ; Nowak, Patrick ; Zölzer, Udo
5	2015	Multicore Reconfiguration Platform - A Research and Evaluation FPGA Framework for Runtime Reconfigurable Systems	Meyer, Dominik
6	2016	Print your gadget: New channels for manufacturers using locally available 3D printers	Klauer, Bernd ; Haase, Jan ; Eckert, Marcel ; Meyer, Dominik
7	2020	Validation and performance anaysis of a parameterizable normalized feedback FxLMS archtiecture for FPGA platforms	Timmermann, Johannes ; Klemd, Alexander ; Hanselka, Jonas ; Sachau, Delf ; Klauer, Bernd